Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor, for example. Types of MOS transistors include NMOS, PMOS and CMOS transistors. The MOS transistor is one of the basic building blocks of most modern electronic circuits.
Typically, semiconductor devices are comprised of millions of transistors formed above a semiconducting substrate. The semiconducting substrate or wafer includes an insulation layer, e.g., a buried oxide layer, above a semiconducting substrate of silicon. Typically, the insulation layer is formed by an oxidation process. Then, a process layer is formed above the insulation layer. The process layer may be formed by a variety of processes, e.g., by a chemical vapor deposition (“CVD”) process.
Shallow trench isolation (STI) structures are provided, e.g., by etching, to create electrically isolated islands or bodies in the process layer. The semiconductor devices are then formed on the bodies of the process layer.
A typical method of fabricating a conventional STI structure in a silicon substrate is shown in FIGS. 1A-1D of the drawings. First, an insulation layer 11 and a process layer 12 are formed on a silicon substrate 10, and then patterned by means of conventional photolithographic and etching process to mask active (device) regions of the substrate. (The active regions are, by definition, the regions of the substrate masked by the insulation layer and the process layer, while the field regions are the regions of the substrate not so masked.) Trenches 13 are then selectively and anisotropically dry-etched in the field (isolation) regions of the substrate 10, as shown in FIG. 1A.
As shown in FIG. 1B, a conformal oxide film 14 is deposited onto the process layer 12 and onto the walls and floor of the trenches 13. The areas of the oxide film 14 which line the trenches 13 serve to repair damage suffered by the substrate when the trenches were etched.
As shown in FIG. 1C, a layer of dielectric 15 is then deposited in a suitable manner, such as by CVD onto the conformal oxide film 14 and within each of the trenches 13. The dielectric can comprise, for example, amorphous SiO2 (known also as fused silica, undoped silica glass, or silica glass) and CVD-polysilicons. As shown in FIG. 1D, the dielectric 15 is etched-back until silica glass remains only within the lined trenches, thus completing fabrication of the trench isolation structures 19, each of which consists of the oxide film 14 (trench liner) within each of the trenches 13 and a dielectric 15 within each of the trench liners 14.
It is well known that tensile stress in the silicon layers surrounding the shallow trench isolation layers affects the mobility of the resulting MOS devices, especially for narrow devices. Increased tensile stress within the silicon layers can improve the mobility of the resulting MOS devices.
What is desired is improved performance of devices to address the ever growing need for improved overall performance. What is still desired is a new and improved shallow trench isolation structure and a method for forming a shallow trench isolation. Preferably, the improved shallow trench isolation structure will provide a desired amount of tensile stress in the surrounding silicon layers so that the mobility of the resulting devices can be improved.